1. Field of the Invention
The present invention relates to a microelectronic device, and more particularly, to a method of fabricating dual damascene interconnections of a microelectronic device.
2. Description of the Related Art
As microelectronic devices become more efficient and highly integrated, multi-layered interconnections are more widely used. To obtain a reliable device including multi-layered interconnections, each interconnection layer are formed in a planar fashion. Thus, dual damascene interconnections have become strongly relied upon.
Meanwhile, in today's highly integrated microelectronic devices, a design rule has been reduced to 0.18 μm or less, and even to 90 nm. Such a small design rule brings about increases in RC delay, cross talk, and power consumption. To solve these problems, an interlayer dielectric (ILD) should be formed of a low-k dielectric material layer. As a result, the need to further develop techniques of fabricating dual damascene interconnections using a low-k ILD has greatly increased.
Methods of fabricating dual damascene interconnections are disclosed in U.S. Pat. No. 6,057,239, and in J. Vac. Sci. Technol. A19 (2001) p. 1388, by P. Jiang et al. However, the method disclosed in U.S. Pat. No. 6,057,239 uses an ILD formed of only an oxide layer, a dielectric constant of which is about 4 to 4.3.
Also, when a trench is etched and cleaned, an etch stop layer may be etched to expose interconnections, thus degrading electrical properties of the interconnections. In the thesis by P. Jiang et al., before a trench is etched, a via is filled with an organic filler, such as a bottom anti-reflection layer (ARL), to prevent degradation of electrical properties. However, because both the organic filler and a photoresist pattern are organic materials having similar etch rates, the photoresist pattern is almost removed during etching of the organic filler formed on an ILD. Thus, when the ILD is etched to form a final trench, the photoresist pattern cannot be used as an etch mask. To prevent this problem, as shown in FIG. 1A, before a photoresist pattern 22 is formed, an organic filler 20 is etched using an etchback process until the organic filler 20 remains only in a via 19. However, this process is very complicated. In addition, as illustrated with dotted circles 24 in FIG. 1B, a low-k ILD 18 is not etched and remains on the organic filler 20 because of a difference in etch rate between the organic filler 20 and the low-k ILD 18. The remaining low-k ILD 18 generates fences 26 as shown in FIG. 1C. In FIGS. 1A and 1B, reference numeral 10 denotes a substrate, 12 denotes a lower ILD, 14 denotes lower interconnections, and 16 denotes an etch stop layer.
To prevent the fence defects, if the organic filler 20 is etched back by over-etching such that a portion of the via 19 is filled with the organic filler 20, a thickness deviation of a photoresist layer becomes very great between a high via-density region and a low via-density region. As a result, a depth of focus (DOF) margin decreases in a photolithographic process.
Further, during an exposure process for forming the photoresist pattern 22, basic materials, such as amine, may be diffused from the ILD 18 through the organic filler 20 to the photoresist layer, thereby resulting in photoresist poisoning.
Therefore, a method of fabricating reliable dual damascene interconnections without degrading electrical properties of a low-k ILD is required.